The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2011
Filed:
Mar. 02, 2007
Ramesha Doddamane, Hyderabad, IN;
Eswar Vadlamani, Hyderabad, IN;
Gopalakrishnan Perur Krishnan, Bangalore, IN;
Tarjinder Singh, Bangalore, IN;
Ramesha Doddamane, Hyderabad, IN;
Eswar Vadlamani, Hyderabad, IN;
Gopalakrishnan Perur Krishnan, Bangalore, IN;
Tarjinder Singh, Bangalore, IN;
Netlogic Microsystems, Inc., Santa Clara, CA (US);
Abstract
A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator () that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store (). An address range selector circuit () can limit the range of addresses generated by an address generator (). Once defective addresses for a first range have been detected, an address range selector circuit () can test another range. An entire address range can thus be tested regardless of the depth of a fault address store ().