The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2011

Filed:

Jan. 12, 2007
Applicants:

Yehiel Gotkis, Fremont, CA (US);

Sergey Lopatin, Morgan Hill, CA (US);

Mehran Nasser-ghodsi, Hamilton, MA (US);

Inventors:

Yehiel Gotkis, Fremont, CA (US);

Sergey Lopatin, Morgan Hill, CA (US);

Mehran Nasser-Ghodsi, Hamilton, MA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2006.01); H01L 21/3205 (2006.01);
U.S. Cl.
CPC ...
Abstract

A first embodiment of the invention relates to a method for evaluating the quality of structures on an integrated circuit wafer. Test structures formed on either on the integrated or on a test wafer are exposed to an electron beam and an electron-beam activated chemical etch. The electron-beam activated etching gas or vapor etches the test structures, which are analyzed after etching to determine a measure of quality of the test structures. The measure of quality may be used in a statistical process control to adjust the parameters used to form device structures on the integrated circuit wafer. The test structures are formed on an integrated circuit wafer having two or more die. Each die has one or more integrated circuit structures. The test structures are formed on scribe lines between two or more adjacent die. Each test structure may correspond in dimensions and/or composition to one or more of the integrated circuit structures.


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