The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2011
Filed:
Aug. 14, 2008
Wagdi W. Abadeer, Jericho, VT (US);
Kiran V. Chatty, Williston, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Jed H. Rankin, Richmond, VT (US);
Robert Robison, Colchester, VT (US);
Yun Shi, South Burlington, VT (US);
William R. Tonti, Essex Junction, VT (US);
Wagdi W. Abadeer, Jericho, VT (US);
Kiran V. Chatty, Williston, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Jed H. Rankin, Richmond, VT (US);
Robert Robison, Colchester, VT (US);
Yun Shi, South Burlington, VT (US);
William R. Tonti, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.