The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2011

Filed:

Oct. 23, 2007
Applicants:

Chang-hoon Jeon, Osan-si, KR;

Satoru Yamada, Seoul, KR;

Sang-yeon Han, Suwon-si, KR;

Jong-man Park, Yonging-si, KR;

Si-ok Sohn, Seoul, KR;

Inventors:

Chang-Hoon Jeon, Osan-si, KR;

Satoru Yamada, Seoul, KR;

Sang-Yeon Han, Suwon-si, KR;

Jong-Man Park, Yonging-si, KR;

Si-Ok Sohn, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/336 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a fin field effect transistor (Fin FET) and a method of manufacturing the Fin FET, the Fin FET includes an active pattern inside which insulating layer patterns are formed, an isolation layer pattern enclosing a sidewall of the active pattern such that an opening exposing a sidewall of the active pattern located between the insulating layer patterns is formed, a gate electrode formed on the active pattern to fill the opening, impurity regions formed at portions of the active pattern adjacent to sidewalls of the gate electrode, an insulating interlayer covering the active pattern and the gate electrode and contact plugs formed through portions of the insulating interlayer and the active pattern adjacent to the sidewalls of the gate electrode such that the contact plug makes contact with the impurity region.


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