The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7935569 B1

PDF
Full Text
Expired
Date of Patent:
May. 03, 2011

Filed:

Oct. 23, 2007
Applicants:

Kyong-mo Bang, San Jose, CA (US);

David Gibson, San Jose, CA (US);

Young-gon Kim, San Jose, CA (US);

John B. Riley, Iii, San Jose, CA (US);

Inventors:

Kyong-Mo Bang, San Jose, CA (US);

David Gibson, San Jose, CA (US);

Young-Gon Kim, San Jose, CA (US);

John B. Riley, III, San Jose, CA (US);

Assignee:

Tessera, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.


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