The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7932165 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 26, 2011

Filed:

Nov. 27, 2006
Applicants:

Charles W. C. Lin, Singapore, SG;

Cheng-chung Chen, Taipei, TW;

Inventors:

Charles W. C. Lin, Singapore, SG;

Cheng-Chung Chen, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of making a semiconductor chip assembly includes providing a metal base, a routing line, a bumped terminal and a filler, wherein the routing line contacts the bumped terminal and the filler, then mechanically attaching a semiconductor chip to the metal base, the routing line, the bumped terminal and the filler, then forming an encapsulant, then etching the metal base to expose the bumped terminal, then etching the bumped terminal to expose the filler, then forming an insulative base, and then grinding the insulative base to expose the filler.


Find Patent Forward Citations

Lin, Charles W. C.. (2011). Method of making a semiconductor chip assembly with a laterally aligned filler and insulative base (U.S. Patent No. 7932165). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7932165

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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