The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2011
Filed:
Oct. 20, 2008
William K. Henson, Peekskill, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Kern Rim, Yorktown Heights, NY (US);
Hsingjen Wann, Kent Lakes, NY (US);
Hung Y. NG, New Milford, NY (US);
William K. Henson, Peekskill, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Kern Rim, Yorktown Heights, NY (US);
Hsingjen Wann, Kent Lakes, NY (US);
Hung Y. Ng, New Milford, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a 'floating' semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.