The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2011

Filed:

Jul. 28, 2009
Applicants:

Hae-jung Yu, Anyang-si, KR;

Eun-chul Ahn, Yongin-si, KR;

Tae-gyeong Chung, Suwon-si, KR;

Nam-seog Kim, Yongin-si, KR;

Inventors:

Hae-Jung Yu, Anyang-si, KR;

Eun-Chul Ahn, Yongin-si, KR;

Tae-Gyeong Chung, Suwon-si, KR;

Nam-Seog Kim, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating an electronic device having stacked chips is provided. The method includes forming a plurality of chips arranged in a row direction and at least one chip arranged in a column direction. A molding layer is formed between the chips. Grooves are formed in the molding layer between the chips arranged in the row direction. Conductive interconnections are formed on the substrate having the grooves. The substrate is sawn along an odd- or even-numbered one of the grooves to be separated into a plurality of unit substrates. At least one of the separated unit substrates is folded along an unsawn groove of the grooves.


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