The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 2011
Filed:
Sep. 10, 2007
Eduard A. Cartier, New York, NY (US);
Rashmi Jha, Wappingers Falls, NY (US);
Sivananda Kanakasabapathy, Niskayuna, NY (US);
Xi LI, Somers, NY (US);
Renee T. MO, Briarcliff Manor, NY (US);
Vijay Narayanan, New York, NY (US);
Vamsi Paruchuri, Albany, NY (US);
Mark T. Robson, Danbury, CT (US);
Kathryn T. Schonenberg, Wappingers Falls, NY (US);
Michelle L. Steen, Danbury, CT (US);
Richard Wise, Newburgh, NY (US);
Ying Zhang, Yorktown Heights, NY (US);
Eduard A. Cartier, New York, NY (US);
Rashmi Jha, Wappingers Falls, NY (US);
Sivananda Kanakasabapathy, Niskayuna, NY (US);
Xi Li, Somers, NY (US);
Renee T. Mo, Briarcliff Manor, NY (US);
Vijay Narayanan, New York, NY (US);
Vamsi Paruchuri, Albany, NY (US);
Mark T. Robson, Danbury, CT (US);
Kathryn T. Schonenberg, Wappingers Falls, NY (US);
Michelle L. Steen, Danbury, CT (US);
Richard Wise, Newburgh, NY (US);
Ying Zhang, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.