The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2011
Filed:
Jun. 22, 2009
Michael W. Konevecki, San Jose, CA (US);
Usha Raghuram, San Jose, CA (US);
Maitreyee Mahajani, Saratoga, CA (US);
Sucheta Nallamothu, San Jose, CA (US);
Andrew J. Walker, Mountain View, CA (US);
Tanmay Kumar, Pleasanton, CA (US);
Michael W. Konevecki, San Jose, CA (US);
Usha Raghuram, San Jose, CA (US);
Maitreyee Mahajani, Saratoga, CA (US);
Sucheta Nallamothu, San Jose, CA (US);
Andrew J. Walker, Mountain View, CA (US);
Tanmay Kumar, Pleasanton, CA (US);
SanDisk 3D LLC, Milpitas, CA (US);
Abstract
The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.