Method of fabricating high-voltage metal oxide semiconductor transistor devices

Abstract

A process of fabricating a transistor employs a relatively thicker sacrificial nitride layer that reduces the time and cost associated with chemical-mechanical polish (CMP) processes by reducing the topography associated with the transistor. The process includes forming the gate oxide region and a field oxide region on a substrate. A polysilicon layer is formed on the gate oxide region and the field oxide region. A sacrificial nitride layer is formed on the polysilicon layer, wherein the sacrificial nitride layer has a thickness approximately equal to or greater than a thickness of the gate oxide region. A polysilicon gate is formed by selectively removing portions of the polysilicon layer and the sacrificial layer to expose a portion of the gate oxide region adjacent to the polysilicon gate. Source/drain regions are formed adjacent to the polysilicon gate using lightly-doped drain (LDD) implantation. A spacer layer is formed over the polysilicon gate and source/drain regions. Portions of the spacer layer are selectively removed, along with the sacrificial nitride layer and the gate oxide region to form sidewall spacers at each end of the polysilicon gate. A pre-metal dielectric layer is formed on the high-voltage MOS transistor, and the pre-metal dielectric layer is planarized.