The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2011

Filed:

Oct. 29, 2009
Applicants:

Wei-yao Lin, Hsinchu County, TW;

Shao-chang Huang, Hsinchu, TW;

Mao-shu Hsu, Hsinchu, TW;

Tang-lung Lee, Taipei County, TW;

Kun-wei Chang, Taipei County, TW;

Inventors:

Wei-Yao Lin, Hsinchu County, TW;

Shao-Chang Huang, Hsinchu, TW;

Mao-Shu Hsu, Hsinchu, TW;

Tang-Lung Lee, Taipei County, TW;

Kun-Wei Chang, Taipei County, TW;

Assignee:

eMemory Technology Inc., Hsinchu Science Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electrostatic discharge (ESD) protection circuit is electrically connected to a core circuit for preventing ESD charges from reaching the core circuit. The ESD protection circuit includes a pad, a pass transistor, a transistor, a capacitor, a resistor, and a delay trigger unit. The pass transistor controls passage of charges from the pad to the core circuit. The transistor sinks ESD charges during an ESD zapping event. The capacitor and the resistor couple voltage at the pad to a control electrode of the transistor for turning on the transistor during the ESD zapping event. The delay trigger unit retards transmission of low voltage to a control electrode of the pass transistor for keeping the pass transistor turned off during the ESD zapping event.


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