The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2011
Filed:
Sep. 04, 2008
Kanji Otsuka, Higashiyamato, JP;
Yutaka Akiyama, Hachiouji, JP;
Kanji Otsuka, Higashiyamato, JP;
Yutaka Akiyama, Hachiouji, JP;
Kyocera Corporation, Kyoto, JP;
Oki Electric Industry Co., Ltd., Tokyo, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Fuji Xerox Co., Ltd., Tokyo, JP;
Fujitsu Microelectronics Limited, Tokyo, JP;
Renesas Technology Corp., Tokyo, JP;
Ibiden Co., Ltd., Gifu, JP;
Kanji Otsuka, Tokyo, JP;
Yutaka Akiyama, Tokyo, JP;
Abstract
A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside.