The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2011

Filed:

Sep. 12, 2005
Applicants:

Eitan Cadouri, Cupertino, CA (US);

Krzysztof A. Kozminski, San Jose, CA (US);

Haifang Liao, San Jose, CA (US);

Kenneth Mednick, San Jose, CA (US);

Roland Ruehl, San Carlos, CA (US);

Mark A. Snowden, Cary, NC (US);

Inventors:

Eitan Cadouri, Cupertino, CA (US);

Krzysztof A. Kozminski, San Jose, CA (US);

Haifang Liao, San Jose, CA (US);

Kenneth Mednick, San Jose, CA (US);

Roland Ruehl, San Carlos, CA (US);

Mark A. Snowden, Cary, NC (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may be performed to provide dynamic performance estimation.


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