The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2011
Filed:
Nov. 28, 2007
Shinichi Tomita, Tokyo, JP;
Masao Yoshimuta, Tokyo, JP;
Yasuyuki Hashimoto, Tokyo, JP;
Akira Nakashima, Tokyo, JP;
Shinichi Tomita, Tokyo, JP;
Masao Yoshimuta, Tokyo, JP;
Yasuyuki Hashimoto, Tokyo, JP;
Akira Nakashima, Tokyo, JP;
Sumco Corporation, Tokyo, JP;
Abstract
A method for manufacturing a silicon wafer is characterized by performing one or both of grinding and polishing to a thin discoid silicon wafer to give bowl-shaped warpage that is concave at a central part to a wafer surface. One main surface of the thin discoid silicon wafer is adsorbed and held, and one or both of grinding and polishing are performed to the other main surface to fabricate a convex wafer whose thickness is increased from a wafer outer periphery toward a wafer center or fabricate a concave wafer whose thickness is reduced from the wafer outer periphery toward the wafer center. Then, the other main surface is adsorbed and held to protrude the center or the periphery of the one main surface side based on elastic deformation. One or both of grinding and polishing are carried out with respect to the one main surface to flatten the main surface, and adsorption and holding are released to give bowl-shaped warpage that is concave at the central part to the other main surface or the one main surface. By the method, an SOI wafer or an epitaxial silicon wafer having a high degree of flatness is obtained.