The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7898076 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 01, 2011

Filed:

Apr. 30, 2007
Applicants:

Bruce Furman, Poughquag, NY (US);

Madhusudan K. Iyengar, Woodstock, NY (US);

Paul A. Lauro, Brewster, NY (US);

Yves Martin, Ossining, NY (US);

Roger R. Schmidt, Poughkeepsie, NY (US);

Da-yuan Shih, Poughkeepsie, NY (US);

Theodore G. Van Kessel, Dutchess County, NY (US);

Wei Zou, Wappingers Falls, NY (US);

Inventors:

Bruce Furman, Poughquag, NY (US);

Madhusudan K. Iyengar, Woodstock, NY (US);

Paul A. Lauro, Brewster, NY (US);

Yves Martin, Ossining, NY (US);

Roger R. Schmidt, Poughkeepsie, NY (US);

Da-Yuan Shih, Poughkeepsie, NY (US);

Theodore G. Van Kessel, Dutchess County, NY (US);

Wei Zou, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

Assemblies for dissipating heat from integrated circuits and circuit chips are disclosed. The assemblies include a low melt solder as a thermal interface material (TIM) for the transfer of heat from a chip to a heat sink (HS), wherein the low melt solder has a melting point below the maximum operating temperature of the chip. Methods for making the assemblies are also disclosed.


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Furman, Bruce. (2011). Structure and methods of processing for solder thermal interface materials for chip cooling (U.S. Patent No. 7898076). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7898076

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