The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2011
Filed:
Apr. 18, 2008
Ta-wen Liao, Hsinchu, TW;
Chih-chun Yang, Hsinchu, TW;
Ming-yuan Huang, Hsinchu, TW;
Han-tu Lin, Hsinchu, TW;
Chih-hung Shih, Hsinchu, TW;
Chin-yueh Liao, Hsinchu, TW;
Chia-chi Tsai, Hsinchu, TW;
Ta-Wen Liao, Hsinchu, TW;
Chih-Chun Yang, Hsinchu, TW;
Ming-Yuan Huang, Hsinchu, TW;
Han-Tu Lin, Hsinchu, TW;
Chih-Hung Shih, Hsinchu, TW;
Chin-Yueh Liao, Hsinchu, TW;
Chia-Chi Tsai, Hsinchu, TW;
Au Optronics Corporation, Hsinchu, TW;
Abstract
A method for fabricating a pixel structure is disclosed. A substrate is provided. A first conductive layer is formed on the substrate, and a first shadow mask exposing a portion of the first conductive layer is disposed over the first conductive layer. Laser is used to irradiate the first conductive layer for removing the part of the first conductive layer and forming a gate. A gate dielectric layer is formed on the substrate to cover the gate. A channel layer is formed on the gate dielectric layer over the gate. A source and a drain are formed on the channel layer and respectively above both sides of the gate. A patterned passivation layer is formed to cover the channel layer and expose the drain. An electrode material layer is formed to cover the patterned passivation layer and the exposed drain.