The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2011

Filed:

Jun. 07, 2007
Applicants:

Bijaya Sahu, Uttar Pradesh, IN;

Abhishek Kanungo, Uttar Pradesh, IN;

Sandeep Pagey, Uttar Pradesh, IN;

Christer Cederberg, St. Paul, MN (US);

Inventors:

Bijaya Sahu, Uttar Pradesh, IN;

Abhishek Kanungo, Uttar Pradesh, IN;

Sandeep Pagey, Uttar Pradesh, IN;

Christer Cederberg, St. Paul, MN (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment, design and verification checksums are calculated for instances of a desired module. The design and verification checksums may be used to further derive hierarchical design and functional checksums. In another embodiment, these checksums are used to merge multiple databases produced by verification runs. In a further embodiment a computing apparatus is provided. The computing apparatus is configured to merge multiple verification databases.


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