The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2011
Filed:
Sep. 19, 2007
Ethan H. Cannon, Essex Junction, VT (US);
Aj Kleinosowski, Austin, TX (US);
K. Paul Muller, Wappingers Falls, NY (US);
Tak H. Ning, Yorktown Heights, NY (US);
Philip J. Oldiges, LaGrangeville, NY (US);
Leon J. Sigal, Monsey, NY (US);
James D. Warnock, Somers, NY (US);
Dieter Wendel, Schoenaich, DE;
Ethan H. Cannon, Essex Junction, VT (US);
AJ KleinOsowski, Austin, TX (US);
K. Paul Muller, Wappingers Falls, NY (US);
Tak H. Ning, Yorktown Heights, NY (US);
Philip J. Oldiges, LaGrangeville, NY (US);
Leon J. Sigal, Monsey, NY (US);
James D. Warnock, Somers, NY (US);
Dieter Wendel, Schoenaich, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.