The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2011
Filed:
Dec. 13, 2005
Lee Wee Teo, Singapore, SG;
Elgin Quek, Singapore, SG;
Dong Kyun Sohn, Singapore, SG;
GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore, SG;
Abstract
A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen to produce a desired amount of stress to improve device performance. In an example embodiment for a tensile stress layer, the PMOS S/D contact area is larger than the NMOS S/D contact area so the tensile stress on the PMOS channel is less than the tensile stress on the NMOS channel. In an example embodiment for a compressive stress layer, the NMOS contact area is larger than the PMOS contact area so that the compressive stress on the NMOS channel is less than the compressive stress on the PMOS channel.