Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom

Abstract

A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness<the second thickness. A substrate having a semiconducting surface is provided. A pad dielectric layer having a thickness≦the second thickness is formed on the semiconductor surface including over the second regions, wherein the pad dielectric layer provides at least a portion of the second thickness for the second gate dielectric. A hard mask layer is formed on the semiconductor surface including over the second regions. A plurality of trench isolation regions are formed by etching through the pad dielectric layer and a portion of the semiconductor surface. The plurality of trench isolation regions are filled with a dielectric fill material to form trench isolation regions, and the hard mask layer is then removed. A patterned gate electrode layer is formed over the second gate dielectric, wherein said patterned gate electrode layer extends over a surface of at least one of the trench isolation regions. Fabrication of the MOS transistors in the first and second regions is then completed.