The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2011

Filed:

Jan. 19, 2010
Applicants:

Alexander L. Minkin, Los Altos, CA (US);

Joel J. Mccormack, Boulder, CO (US);

Paul S. Heckbert, Pittsburgh, PA (US);

Michael J. M. Toksvig, Palo Alto, CA (US);

Luke Y. Chang, San Mateo, CA (US);

Karim Abdalla, Menlo Park, CA (US);

BO Hong, Fremont, CA (US);

John W. Berendsen, Beaconsfield, CA;

Walter Donavan, Saratoga, CA (US);

Emmett M. Kilgariff, San Jose, CA (US);

Inventors:

Alexander L. Minkin, Los Altos, CA (US);

Joel J. McCormack, Boulder, CO (US);

Paul S. Heckbert, Pittsburgh, PA (US);

Michael J. M. Toksvig, Palo Alto, CA (US);

Luke Y. Chang, San Mateo, CA (US);

Karim Abdalla, Menlo Park, CA (US);

Bo Hong, Fremont, CA (US);

John W. Berendsen, Beaconsfield, CA;

Walter Donavan, Saratoga, CA (US);

Emmett M. Kilgariff, San Jose, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 17/00 (2006.01); G06T 11/40 (2006.01); G09G 5/00 (2006.01); G09G 5/02 (2006.01); G06K 9/40 (2006.01); G06K 9/32 (2006.01); G06K 9/64 (2006.01);
U.S. Cl.
CPC ...
Abstract

Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.


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