The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2011
Filed:
Oct. 31, 2008
Tom Zhong, Saratoga, CA (US);
Chyu-jiuh Torng, Pleasanton, CA (US);
Rongfu Xiao, Fremont, CA (US);
Adam Zhong, Milpitas, CA (US);
Wai-ming Johnson Kan, San Ramon, CA (US);
Daniel Liu, San Jose, CA (US);
Tom Zhong, Saratoga, CA (US);
Chyu-Jiuh Torng, Pleasanton, CA (US);
Rongfu Xiao, Fremont, CA (US);
Adam Zhong, Milpitas, CA (US);
Wai-Ming Johnson Kan, San Ramon, CA (US);
Daniel Liu, San Jose, CA (US);
MagIC Technologies, Inc., Milpitas, CA (US);
Abstract
A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.