The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2011
Filed:
Dec. 01, 2008
Mu-yi Liu, Taichung, TW;
Chia-lun Hsu, Taipei, TW;
Ichen Yang, Changhua, TW;
Kuan-po Chen, Taipei, TW;
Tao-cheng LU, Hsinchu, TW;
Mu-Yi Liu, Taichung, TW;
Chia-Lun Hsu, Taipei, TW;
Ichen Yang, Changhua, TW;
Kuan-Po Chen, Taipei, TW;
Tao-Cheng Lu, Hsinchu, TW;
Macronix International Co., Ltd., Hsinchu, TW;
Abstract
An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.