The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2011

Filed:

Jul. 21, 2008
Applicants:

Xiangdong Chen, Poughquag, NY (US);

Jong Ho Lee, Fishkill, NY (US);

Weipeng LI, Beacon, NY (US);

Dae-gyu Park, Poughquag, NY (US);

Kenneth J. Stein, Sandy Hook, CT (US);

Voon-yew Thean, Fishkill, NY (US);

Inventors:

Xiangdong Chen, Poughquag, NY (US);

Jong Ho Lee, Fishkill, NY (US);

Weipeng Li, Beacon, NY (US);

Dae-Gyu Park, Poughquag, NY (US);

Kenneth J. Stein, Sandy Hook, CT (US);

Voon-Yew Thean, Fishkill, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).


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