The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2011
Filed:
May. 15, 2008
Lloyd G. Burrell, Poughkeepsie, NY (US);
Howard Hao Chen, Yorktown Heights, NY (US);
Louis L. Hsu, Fishkill, NY (US);
Wolfgang Sauter, Richmond, VT (US);
Lloyd G. Burrell, Poughkeepsie, NY (US);
Howard Hao Chen, Yorktown Heights, NY (US);
Louis L. Hsu, Fishkill, NY (US);
Wolfgang Sauter, Richmond, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.