The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2011

Filed:

Nov. 16, 2007
Applicants:

Georg Pietsch, Burghausen, DE;

Michael Kerstan, Burghausen, DE;

Werner Blaha, Altötting, DE;

Inventors:

Georg Pietsch, Burghausen, DE;

Michael Kerstan, Burghausen, DE;

Werner Blaha, Altötting, DE;

Assignee:

Siltronic AG, Munich, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B24B 49/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to a process for producing a semiconductor wafer by double-side grinding of the semiconductor wafer, in which the semiconductor wafer is simultaneously ground on both sides, first by rough-grinding and then by finish-grinding, using a grinding tool. The semiconductor wafer, between the rough-grinding and the finish-grinding, remains positioned in the grinding machine, and the grinding tool continues to apply a substantially constant load during the transition from rough-grinding to finish-grinding. The invention also relates to an apparatus for carrying out the process and to a semiconductor wafer having a local flatness value on a front surface of less than 16 nm in a measurement window of 2 mm×2 mm area and of less than 40 nm in a measurement window of 10 mm×10 mm area.


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