The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2011

Filed:

Jan. 05, 2009
Applicant:

Robert Strain, San Jose, CA (US);

Inventor:

Robert Strain, San Jose, CA (US);

Assignee:

Semi Solutions, LLC., Los Gatos, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2006.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01);
U.S. Cl.
CPC ...
Abstract

Deep submicron wells of MOS transistors, implemented over an ungrounded well, exhibit two modes of operation: a current sink mode and a current source mode. While operation as a current sink is well understood and successfully controlled, it is also necessary to control the current provided in the current source mode of the well. A Schottky diode is connected between the well and the gate, the Schottky diode having a smaller barrier height than that of the PN junction of the well-to-source. For an NMOS transistor, current flows through the PN junction when the gate is high. When the gate is low, current flows through the Schottky diode. This difference of current flow results in a difference in transistor threshold, thereby achieving a dynamic threshold voltage using the current from the well when operating at the current source mode.


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