The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2011

Filed:

Feb. 13, 2008
Applicants:

Denis A. Masliah, St-Germain en Laye, FR;

Alexandre G. Bracale, Paris, FR;

Francis C. Huin, Soullans, FR;

Patrice J. Barroul, Bois d'Arcy, FR;

Inventors:

Denis A. Masliah, St-Germain en Laye, FR;

Alexandre G. Bracale, Paris, FR;

Francis C. Huin, Soullans, FR;

Patrice J. Barroul, Bois d'Arcy, FR;

Assignee:

ACCO Semiconductor Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A double-gate semiconductor device provides a high breakdown voltage allowing for a large excursion of the output voltage that is useful for power applications. The double-gate semiconductor device may be considered a double-gate device including a MOS gate and a junction gate, in which the bias of the junction gate may be a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. Because an individual junction gate has an intrinsically high breakdown voltage, the breakdown voltage of the double-gate semiconductor device is greater than the breakdown voltage of an individual MOS gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices. The double-gate semiconductor device may also be fabricated in a higher spatial density configuration such that a common implantation between the MOS gate and the junction gate is eliminated.


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