The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2011

Filed:

Jun. 26, 2009
Applicants:

Shimpei Tsujikawa, Tokyo, JP;

Yasuhiko Akamatsu, Tokyo, JP;

Hiroshi Umeda, Tokyo, JP;

Jiro Yugami, Tokyo, JP;

Masaharu Mizutani, Tokyo, JP;

Masao Inoue, Tokyo, JP;

Junichi Tsuchimoto, Tokyo, JP;

Kouji Nomura, Hyogo, JP;

Inventors:

Shimpei Tsujikawa, Tokyo, JP;

Yasuhiko Akamatsu, Tokyo, JP;

Hiroshi Umeda, Tokyo, JP;

Jiro Yugami, Tokyo, JP;

Masaharu Mizutani, Tokyo, JP;

Masao Inoue, Tokyo, JP;

Junichi Tsuchimoto, Tokyo, JP;

Kouji Nomura, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.


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