The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2011
Filed:
Aug. 25, 2008
Ricky Amos, Rhinebeck, NY (US);
Douglas A. Buchanan, Cortlandt Manor, NY (US);
Cyril Cabral, Jr., Ossining, NY (US);
Alessandro C. Callegari, Yorktown Heights, NY (US);
Supratik Guha, Chappaqua, NY (US);
Hyungjun Kim, Fishkill, NY (US);
Fenton R. Mcfeely, Ossining, NY (US);
Vijay Narayanan, New York, NY (US);
Kenneth P. Rodbell, Sandy Hook, CT (US);
John J. Yurkas, Stamford, CT (US);
Ricky Amos, Rhinebeck, NY (US);
Douglas A. Buchanan, Cortlandt Manor, NY (US);
Cyril Cabral, Jr., Ossining, NY (US);
Alessandro C. Callegari, Yorktown Heights, NY (US);
Supratik Guha, Chappaqua, NY (US);
Hyungjun Kim, Fishkill, NY (US);
Fenton R. McFeely, Ossining, NY (US);
Vijay Narayanan, New York, NY (US);
Kenneth P. Rodbell, Sandy Hook, CT (US);
John J. Yurkas, Stamford, CT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO, AlOand other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re(CO)as the source material is used when Re is to be deposited.