The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2010

Filed:

Nov. 02, 2007
Applicants:

Gary D. Grise, Colchester, VT (US);

Peter A. Habitz, Hinesburg, VT (US);

Vikram Iyengar, S. Burlington, VT (US);

David E. Lackey, Jericho, VT (US);

Chandramouli Visweswariah, Croton-on-Hudson, NY (US);

Vladimir Zolotov, Putnam Valley, NY (US);

Inventors:

Gary D. Grise, Colchester, VT (US);

Peter A. Habitz, Hinesburg, VT (US);

Vikram Iyengar, S. Burlington, VT (US);

David E. Lackey, Jericho, VT (US);

Chandramouli Visweswariah, Croton-on-Hudson, NY (US);

Vladimir Zolotov, Putnam Valley, NY (US);

Assignee:

International Business Machines Corporation, New Orchard Rd., Armonk, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.


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