The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2010

Filed:

Mar. 02, 2010
Applicants:

Charles F. Carey, Endicott, NY (US);

Bernt Julius Hansen, Afton, NY (US);

Ashwani K. Malhotra, Lagrangeville, NY (US);

David L. Questad, Hopewell Junction, NY (US);

Wolfgang Sauter, Richmond, VT (US);

Inventors:

Charles F. Carey, Endicott, NY (US);

Bernt Julius Hansen, Afton, NY (US);

Ashwani K. Malhotra, Lagrangeville, NY (US);

David L. Questad, Hopewell Junction, NY (US);

Wolfgang Sauter, Richmond, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor chip for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.


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