The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2010

Filed:

Jul. 03, 2008
Applicants:

Ichiro Mizushima, Yokohama, JP;

Hirokazu Ishida, Yokohama, JP;

Yoshio Ozawa, Yokohama, JP;

Takashi Suzuki, Yokohama, JP;

Fumiki Aiso, Yokohama, JP;

Makoto Mizukami, Kawasaki, JP;

Inventors:

Ichiro Mizushima, Yokohama, JP;

Hirokazu Ishida, Yokohama, JP;

Yoshio Ozawa, Yokohama, JP;

Takashi Suzuki, Yokohama, JP;

Fumiki Aiso, Yokohama, JP;

Makoto Mizukami, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a method of manufacturing a semiconductor memory device, an opening is made in a part of an insulating film formed on a silicon substrate. An amorphous silicon thin film is formed on the insulating film in which the opening has been made and inside the opening. Then, a monocrystal is solid-phase-grown in the amorphous silicon thin film, with the opening as a seed, thereby forming a monocrystalline silicon layer. Then, the monocrystalline silicon layer is heat-treated in an oxidizing atmosphere, thereby thinning the monocrystalline silicon layer and reducing the defect density. Then, a memory cell array is formed on the monocrystalline silicon layer which has been thinned and whose defect density has been reduced.


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