The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2010

Filed:

Nov. 15, 2006
Applicants:

Takashi Ozawa, Nagano, JP;

Yasushi Araki, Nagano, JP;

Masatoshi Nakamura, Nagano, JP;

Seiji Sato, Nagano, JP;

Inventors:

Takashi Ozawa, Nagano, JP;

Yasushi Araki, Nagano, JP;

Masatoshi Nakamura, Nagano, JP;

Seiji Sato, Nagano, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A mounting substrate for mounting a semiconductor chip in a flip chip manner, having a plurality of connection pads to which the semiconductor chip is connected, an insulating pattern formed so as to cover a part of the connection pads, and a plurality of dummy patterns for controlling a flow of an underfill infiltrated below the semiconductor chip, characterized in that the plurality of dummy patterns are arranged in staggered lattice shape.


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Ozawa, Takashi. (2010). Mounting substrate and semiconductor device (U.S. Patent No. 7838998). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7838998

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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