The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2010

Filed:

Oct. 26, 2007
Applicants:

James W. Adkisson, Jericho, VT (US);

Natalie B. Feilchenfeld, Jericho, VT (US);

Jeffrey P. Gambino, Westford, VT (US);

Benjamin T. Voegeli, Burlington, VT (US);

Michael J. Zierak, Essex Junction, VT (US);

Inventors:

James W. Adkisson, Jericho, VT (US);

Natalie B. Feilchenfeld, Jericho, VT (US);

Jeffrey P. Gambino, Westford, VT (US);

Benjamin T. Voegeli, Burlington, VT (US);

Michael J. Zierak, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/331 (2006.01);
U.S. Cl.
CPC ...
Abstract

A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protected from thermal oxidation. A thermal oxide on the drain side sidewall of the gate electrode is integrally formed with a graded thickness silicon oxide containing gate dielectric, of which the thickness monotonically increases from the source side to the drain side. The thickness profile may be self-aligned to the drain side edge of the gate electrode, or may have a portion with a self-limiting thickness. The graded thickness profile may be advantageously used to form a lateral diffusion metal oxide semiconductor field effect transistor providing an enhanced performance.


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