The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 2010
Filed:
Jul. 18, 2008
Han-byung Park, Seongnam-si, KR;
Soon-moon Jung, Seongnam-si, KR;
Hoon Lim, Seoul, KR;
Cha-dong Yeo, Suwon-si, KR;
Byoung-keun Son, Suwon-si, KR;
Jae-joo Shim, Suwon-si, KR;
Chang-min Hong, Seoul, KR;
Han-Byung Park, Seongnam-si, KR;
Soon-Moon Jung, Seongnam-si, KR;
Hoon Lim, Seoul, KR;
Cha-Dong Yeo, Suwon-si, KR;
Byoung-Keun Son, Suwon-si, KR;
Jae-Joo Shim, Suwon-si, KR;
Chang-Min Hong, Seoul, KR;
Samsung Electronics Co., Ltd., Gyeonggi-Do, KR;
Abstract
A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.