The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2010
Filed:
Mar. 31, 2009
Konstantin V. Loiko, Austin, TX (US);
Cheong M. Hong, Austin, TX (US);
Sung-taeg Kang, Austin, TX (US);
Taras A. Kirichenko, Austin, TX (US);
Brian A. Winstead, Austin, TX (US);
Konstantin V. Loiko, Austin, TX (US);
Cheong M. Hong, Austin, TX (US);
Sung-Taeg Kang, Austin, TX (US);
Taras A. Kirichenko, Austin, TX (US);
Brian A. Winstead, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate.