The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 2010
Filed:
Apr. 18, 2008
Kuo-lung Fang, Hsinchu, TW;
Chih-chun Yang, Hsinchu, TW;
Ming-yuan Huang, Hsinchu, TW;
Han-tu Lin, Hsinchu, TW;
Chih-hung Shih, Hsinchu, TW;
Ta-wen Liao, Hsinchu, TW;
Shiun-chang Jan, Hsinchu, TW;
Chia-chi Tsai, Hsinchu, TW;
Kuo-Lung Fang, Hsinchu, TW;
Chih-Chun Yang, Hsinchu, TW;
Ming-Yuan Huang, Hsinchu, TW;
Han-Tu Lin, Hsinchu, TW;
Chih-Hung Shih, Hsinchu, TW;
Ta-Wen Liao, Hsinchu, TW;
Shiun-Chang Jan, Hsinchu, TW;
Chia-Chi Tsai, Hsinchu, TW;
Au Optronics Corporation, Hsinchu, TW;
Abstract
A method for fabricating a pixel structure includes following steps. First, a substrate is provided. Next, a first conductive layer is formed on the substrate. Next, a first shadow mask is disposed over the first conductive layer. Next, a laser is applied through the first shadow mask to irradiate the first conductive layer to form a gate. Next, a gate dielectric layer is formed on the substrate to cover the gate. After that, a channel layer, a source and a drain are simultaneously formed on the gate dielectric layer over the gate, wherein the gate, the channel layer, the source and the drain together form a thin film transistor. A patterned passivation layer is formed on the thin film transistor and the patterned passivation layer exposes a part of the drain. Furthermore, a pixel electrode electrically connecting to the drain is formed.