The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2010
Filed:
May. 19, 2009
Chung-long Cheng, Hsinchu, TW;
Kong-beng Thei, Hsinchu, TW;
Sheng-chen Chung, Hsinchu, TW;
Tzung-chi Lee, Hsinchu, TW;
Harry Chuang, Austin, TX (US);
Chung-Long Cheng, Hsinchu, TW;
Kong-Beng Thei, Hsinchu, TW;
Sheng-Chen Chung, Hsinchu, TW;
Tzung-Chi Lee, Hsinchu, TW;
Harry Chuang, Austin, TX (US);
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.