The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2010

Filed:

Jan. 13, 2006
Applicants:

Marius K. Orlowski, Austin, TX (US);

Olubunmi O. Adetutu, Austin, TX (US);

Phillip J. Stout, Austin, TX (US);

Inventors:

Marius K. Orlowski, Austin, TX (US);

Olubunmi O. Adetutu, Austin, TX (US);

Phillip J. Stout, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack () formed over a substrate (), thereby forming an etched gate () having a vertical sidewall profile (). By constructing the gate stack () with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile () may be obtained.


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