The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2010
Filed:
Jun. 23, 2005
Muraleedhara H. Navada, Santa Clara, CA (US);
Tim Frodsham, Portland, OR (US);
Sanjay Dabral, Palo Alto, CA (US);
Allen Baum, Palo Alto, CA (US);
Chris D. Matthews, Folsom, CA (US);
Chris C. Gianos, Sterling, MA (US);
Rahul R. Shah, Marlborough, MA (US);
Theodore Z. Schoenborn, Portland, OR (US);
Muraleedhara H. Navada, Santa Clara, CA (US);
Tim Frodsham, Portland, OR (US);
Sanjay Dabral, Palo Alto, CA (US);
Allen Baum, Palo Alto, CA (US);
Chris D. Matthews, Folsom, CA (US);
Chris C. Gianos, Sterling, MA (US);
Rahul R. Shah, Marlborough, MA (US);
Theodore Z. Schoenborn, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.