The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2010
Filed:
Jul. 20, 2006
Ted R. White, Austin, TX (US);
Leo Mathew, Austin, TX (US);
Bich-yen Nguyen, Austin, TX (US);
Zhonghai Shi, Austin, TX (US);
Voon-yew Thean, Austin, TX (US);
Mariam G. Sadaka, Austin, TX (US);
Ted R. White, Austin, TX (US);
Leo Mathew, Austin, TX (US);
Bich-Yen Nguyen, Austin, TX (US);
Zhonghai Shi, Austin, TX (US);
Voon-Yew Thean, Austin, TX (US);
Mariam G. Sadaka, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer () that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer () by a buried insulator layer (); forming an STI region () in the second semiconductor layer () and buried insulator layer (); exposing the first semiconductor layer () in a first area () of a STI region (); epitaxially growing a first epitaxial semiconductor layer () from the exposed first semiconductor layer (); and selectively etching the first epitaxial semiconductor layer () and the second semiconductor layer () to form CMOS FinFET channel regions (e.g.,) and planar channel regions (e.g.,) from the first epitaxial semiconductor layer () and the second semiconductor layer ().