The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 2010
Filed:
Jan. 18, 2006
Samuel J. Anderson, Tempe, AZ (US);
David N. Okada, Chandler, AZ (US);
Samuel J. Anderson, Tempe, AZ (US);
David N. Okada, Chandler, AZ (US);
Great Wall Semiconductor Corporation, Tempe, AZ (US);
Abstract
A chip-scale package houses a monolithic semiconductor die containing first and second lateral metal oxide semiconductor field effect transistors (MOSFETs) formed on a surface of the semiconductor die. The MOSFETs are formed using a lateral double diffused metal oxide semiconductor structure. The first MOSFET has a first conduction terminal coupled to a first package terminal and a second conduction terminal coupled to a second package terminal. The second MOSFET has a first conduction terminal coupled to a control terminal of the first MOSFET, a second conduction terminal coupled to a third package terminal, and a control terminal coupled to a fourth package terminal. A resistor is coupled between the first package terminal and the control terminal of the first MOSFET. A logic level enable signal controls the first MOSFET to enable the second MOSFET to connect a DC voltage from the first package terminal to the second package terminal.