The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 2010
Filed:
Oct. 24, 2007
Yuniarto Widjaja, San Jose, CA (US);
Henry A. O'm'mani, Milpitas, CA (US);
Prateep Tuntasood, San Jose, CA (US);
Bomy Chen, Cupertino, CA (US);
Yuniarto Widjaja, San Jose, CA (US);
Henry A. O'M'Mani, Milpitas, CA (US);
Prateep Tuntasood, San Jose, CA (US);
Bomy Chen, Cupertino, CA (US);
Silicon Storage Technology, Inc., Sunnyvale, CA (US);
Abstract
A plurality of non-volatile memory cell units are arranged in rows and columns in a single crystalline semiconductor substrate of a first conductivity type. Each cell unit has a first region of a second conductivity type in the substrate along the planar surface, and a second region of the second conductivity, spaced apart from the first region, with a channel region therebetween. The channel region has a first portion adjacent to the first region, a third portion adjacent to the second region and a second portion therebetween. A first and second floating gates are over the first portion and third portion respectively and are insulated therefrom. A first and second control gates are over the first and second floating gates respectively and are capacitively coupled thereto. A first and second erase gates are over the first and second regions respectively and are insulated therefrom. A word line is over the second portion and is insulated therefrom. Electrical contacts to the array are made along the extremities of the array.