The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
Jul. 13, 2007
Kwon Whan Han, Seoul, KR;
Chang Jun Park, Gyeonggi-do, KR;
Min Suk Suh, Seoul, KR;
Seong Cheol Kim, Gyeongsangnam-do, KR;
Sung Min Kim, Seoul, KR;
Seung Taek Yang, Seoul, KR;
Seung Hyun Lee, Gyeonggi-do, KR;
Jong Hoon Kim, Gyeonggi-do, KR;
Ha NA Lee, Seoul, KR;
Kwon Whan Han, Seoul, KR;
Chang Jun Park, Gyeonggi-do, KR;
Min Suk Suh, Seoul, KR;
Seong Cheol Kim, Gyeongsangnam-do, KR;
Sung Min Kim, Seoul, KR;
Seung Taek Yang, Seoul, KR;
Seung Hyun Lee, Gyeonggi-do, KR;
Jong Hoon Kim, Gyeonggi-do, KR;
Ha Na Lee, Seoul, KR;
Hynix Semiconductor Inc., Kyoungki-do, KR;
Abstract
A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.