The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
Jan. 31, 2006
Masami Akimoto, Koshi, JP;
Shinichi Hayashi, Koshi, JP;
Yasushi Hayashida, Koshi, JP;
Nobuaki Matsuoka, Koshi, JP;
Yoshio Kimura, Koshi, JP;
Issei Ueda, Koshi, JP;
Hikaru Ito, Minato-ku, JP;
Masami Akimoto, Koshi, JP;
Shinichi Hayashi, Koshi, JP;
Yasushi Hayashida, Koshi, JP;
Nobuaki Matsuoka, Koshi, JP;
Yoshio Kimura, Koshi, JP;
Issei Ueda, Koshi, JP;
Hikaru Ito, Minato-ku, JP;
Tokyo Electron Limited, Tokyo-To, JP;
Abstract
Provided is a coating and developing apparatus composed of an assembly of plural unit blocks. A first unit-block stack and a second unit-block stack are arranged at different positions with respect to front-and-rear direction. Unit blocks for development, each of which comprises plural processing units including a developing unit that performs developing process after exposure and a transfer device that transfers a substrate among the processing units, are arranged at the lowermost level. Unit blocks for application, or coating, each of which comprises plural processing units including a coating unit that performs application process before exposure and a transfer device that transfers a substrate among the processing units, are arranged above the unit blocks for development. Unit blocks for application are arranged in both the first and second unit-block stacks. Unit blocks for application which a wafer goes through are determined depending on the layering positional relationship between an antireflective film and a resist film. An exposed wafer goes only through the unit block for development without going through any one of the unit blocks for application.