The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2010
Filed:
Jan. 24, 2008
Brad Sharpe-geisler, San Jose, CA (US);
OM P. Agrawal, Los Altos, CA (US);
Kiet Truong, San Jose, CA (US);
Giap Tran, San Jose, CA (US);
Bai Nguyen, Union City, CA (US);
Brad Sharpe-Geisler, San Jose, CA (US);
Om P. Agrawal, Los Altos, CA (US);
Kiet Truong, San Jose, CA (US);
Giap Tran, San Jose, CA (US);
Bai Nguyen, Union City, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
Within a programmable logic device, a multi-data rate SDRAM interface such as a DDR SDRAM interface includes in one embodiment a DQS clock tree, a slave delay circuit, and a delay-locked loop (DLL). The slave delay circuit is adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, and the DLL is adapted to control the slave delay circuit. The DLL includes a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.