The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2010

Filed:

Mar. 24, 2008
Applicants:

Huilong Zhu, Poughkeepsie, NY (US);

Bruce B. Doris, Brewster, NY (US);

Xinlin Wang, Poughkeepsie, NY (US);

Jochen Beintner, Wappingers Falls, NY (US);

Ying Zhang, Yorktown Heights, NY (US);

Philip J. Oldiges, Lagrangeville, NY (US);

Inventors:

Huilong Zhu, Poughkeepsie, NY (US);

Bruce B. Doris, Brewster, NY (US);

Xinlin Wang, Poughkeepsie, NY (US);

Jochen Beintner, Wappingers Falls, NY (US);

Ying Zhang, Yorktown Heights, NY (US);

Philip J. Oldiges, Lagrangeville, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.


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