The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2010
Filed:
Jul. 12, 2006
Kuei Shun Chen, Hsin-Chu, TW;
Chin-hsiang Lin, Hsin-Chu, TW;
Vencent Chang, Hsinchu, TW;
Lawrence Lin, Zhubei, TW;
Lai Chien Wen, Hsinchu, TW;
Jhun Hua Chen, Chang Hua, TW;
Kuei Shun Chen, Hsin-Chu, TW;
Chin-Hsiang Lin, Hsin-Chu, TW;
Vencent Chang, Hsinchu, TW;
Lawrence Lin, Zhubei, TW;
Lai Chien Wen, Hsinchu, TW;
Jhun Hua Chen, Chang Hua, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).